This invention relates to a receiver for an optical communications system, and in particular to clock recovery in a Dual Polarisation Quadrature Phase Shift Keying System.
Two principle forms of modulation are utilised in optical communications systems; Amplitude Shift Keying (ASK) and Phase Shift Keying (PSK), which encode data in the amplitude and phase, respectively, of the transmitted light. Direct detection methods can be utilised to detect and receive ASK signals, but not PSK signals in which the data cannot be recovered from the power envelope of the light. Coherent detection, in which the received light is mixed with an optical Local Oscillator (LO), enables the reception of PSK signals.
The optical LO may be locked to the frequency and phase of the incoming optical signal (homodyne reception), or, may be held very close to, but not locked precisely to, the incoming optical signal (intradyne reception), or may be at a significantly different frequency in relation to the incoming optical signal (heterodyne reception). Locking an optical LO to an incoming signal for a homodyne system presents many practical difficulties in the optical implementation, while heterodyne reception requires the use of high frequency electronics to remove the frequency offset. Intradyne reception offers a compromise where control of the optical LO is relatively easy to achieve, and the bandwidth of the electrical signal is kept to frequencies which are also relatively simple to manage and process.
A particular form of PSK is Quadrature PSK (QPSK) in which two bits are encoded per symbol. The symbol rate of a QPSK signal is thus half the bit rate carried by the signal. FIG. 1 shows power 10 and electrical field 11 eyes of a QPSK signal. As can be seen, the optical power of each symbol is the same, with the information residing in the optical phase of the signal. Variations in the optical power envelope are caused by transitions between symbols and do not convey any information.
Light sources used for optical transmission systems are generally well-polarised lasers. Independently modulated sources can thus be polarisation multiplexed for transmission, thereby transmitting four bits per symbol at a single wavelength in a Dual Polarisation QPSK (DP-QPSK) format. In a DP-QPSK signal the power and field eyes shown in FIG. 1 are repeated independently, although usually aligned in time at the transmitter, on each polarisation.
A DP-QPSK optical signal is conveniently generated from 4 independent data signals, each at the symbol rate. A 40 Gb/s DP-QPSK signal can thus be generated from four 10 Gb/s electrical signals, thereby utilising relatively cheap 10 Gb/s electrical components. FIG. 2 shows a schematic diagram of a DP-QPSK modulator driven by four signals 20-23, at the symbol rate.
FIG. 3 shows an example of a receiver for receiving a DP-QPSK signal. The received signal 30 is split into two orthogonal polarisations by polarisation beam splitter 31 and each signal is fed to a 90° optical hybrid 32, 33. An optical LO 34 is also fed to each hybrid 32, 33 for mixing with the data signals. The outputs of each hybrid are passed to separate photodetectors 35a, b, c, d to convert their amplitudes to electrical signals which are converted to digital values by Analogue to Digital Converters (ADCs) 36a, b, c, d. Those values are passed to ASIC 37 for digital signal processing.
The outputs from the photodiodes can be expressed as shown below.Vx0=|Esx+ELO|2=|Esx|2+|ELO|2+2e{EsxELO*}Vx90=|Esx+jELO|2=|Esx|2+|ELO|2+2ℑm{EsxELO*}Vy0=|Esy+ELO|2=|Esy|2+|ELO|2+2e{EsyELO*}Vy90=|Esy+jELO|2=|Esy|2+|ELO|2+2ℑm{EsyELO*}
The first two terms on the right in each equation are small, or can be removed by electrical components, leaving the detected signals represented by the right hand term on each line. Each of the electrical signals passed to ASIC 37 thus represent a combination of the data signal and the optical LO. The ASIC must therefore remove the residual LO from the signals to enable decoding of the data.
Optical signals suffer distortion during their transmission, for example due to Chromatic dispersion. It is known that Finite Impulse Response (FIR) filters are effective at removing linear dispersions such as Chromatic Dispersion (CD) (see, for example, J. H. Winters, “Equalization in Coherent Lightwave Systems Using a Fractionally Spaced Equalizer”, JLT, Vol. 8, No. 10, October 1990 and Taylor, M. (2004), ‘Coherent detection method using DSP for demodulation of signal and subsequent equalization of propagation impairments’, Photonics Technology Letters, IEEE 16(2), 674-676.), both of which are incorporated herein by reference. FIG. 4 shows a simplified block diagram of a receiver for a single polarisation utilizing an FIR filter 40 to correct distortion and a carrier recovery block 41 to remove the residual LO offset signal.
After correction by the FIR filter 40 the symbols are discrete, but located at arbitrary phases (as shown at 42) due to the LO offset. The carrier recovery block 41 removes that offset resulting in the phases lying on the expected constellation 43 for a QPSK signal.
FIG. 5 shows an example configuration of a FIR filter 40, implemented as is known in the art.
During transmission the polarisation of the optical signal is rotated and may be received in any arbitrary alignment, not necessarily aligned with the receiver as has been assumed above. A butterfly structure of FIR filters may be utilised to process the received signals when the polarisation is in an unknown state. FIG. 6 shows a filter structure for performing this demultiplexing as described in, for example, Savory et al., “Digital Equalisation of 40 Gbit/s per Wavelength Transmission over 2480 km of Standard Fibre without Optical Dispersion Compensation”, ECOC2006, Paper 2.5.5, 2006, incorporated herein by reference.
FIG. 7 shows a block diagram of a digital receiver system for an optical communications system. As explained above, the input signal 70 is mixed with a local oscillator in block 32 and fed to a set of four photodiodes 35. The outputs of the photodiodes are digitised in ADCs 36, the output being passed to a digital processing system 71. The digital processing system 71 is typically provided by a CMOS Application Specific Integrated Circuit (ASIC) specifically designed to process the digitised signals including an equaliser 74 to correct distortion, but may be any system suitable for performing the tasks required, for example a DSP may be appropriate. The processing system processes the data in real time and therefore must be capable of operating on the full data payload. For example, a typical receiver may receive a 10-40 Gb/s signal for processing. ASICs provide convenient systems for performing this processing as they allow the design of a highly parallel system to cope with processing such high data rates.
The ADCs and processing system and other components may be provided by a single device, or separated between different devices as appropriate. The same or different type of device may be appropriate for each function.
The data clock frequency and phase of the incoming signal must be derived such that the ADCs can sample the incoming signal at the correct point and sample rate. A conventional approach, as shown in FIG. 7, is to use an analogue Phase Locked Loop (PLL) formed of phase detector 73 and Voltage Controlled Oscillator (VCO) 72. Although not shown explicitly, it will be appreciated that a loop filter will be incorporated in the PLL. It is generally convenient to locate this in close proximity to the VCO and it may therefore be considered to form part of the VCO block 72 in FIG. 7. However, the incoming signal may be so distorted that this system cannot track the signal to acquire the clock phase. For example, the distortion correction may tolerate 10,000-20,000 ps/nm of dispersion which is significantly higher than conventional analogue PLLs have been shown to work over.
An alternative method shown in FIG. 8 is to utilise a digital phase detector 80 operating from the equalised signals to control the VCO 72. In order to meet certain telecommunications standards (for example G.8251) a PLL bandwidth of greater than 1 MHz may be required. However, the correction system 74 introduces delay into the PLL which affects operation. In particular, gain peaking is introduced making it extremely difficult, if not impossible, to meet the performance required by the standards. The processor may require 10-40 clock cycles to perform the equalisation process and typically operates at 300-600 MHz giving 30-100 ns of delay in the feedback loop which is sufficient to degrade the performance of a 1 MHz PLL. FIG. 9 shows a Jitter mask demonstrating the effect of delay on the PLL of FIG. 8 with a 1 MHz bandwidth. Performance is reduced to below the required level even with 16 clock cycles of delay in the loop. In contrast, in similar implementations in the radio domain the processing rate is far higher than the data rate, making the delay less significant to the operation of the feedback loop.
There is therefore a requirement for a clock recovery system that can perform clock recovery from a highly distorted signal, such as an uncompensated DP-QPSK signal.
The startup of an optical transmission system receiver may be difficult, or impossible. The clock recovery and compensation systems are inter-dependent and one cannot begin operation without the other being at least partially operational. There is therefore a need for a method which can initialise the receiver in such a system.